## March 2019 – What's the Worst That Can Happen? Thoughts on Worst Case Circuit Analysis

When you design a circuit, you try to meet your target requirements as closely as possible. You model the circuit, putting in the exact values for every component used to get an output that matches your requirements. Done, right?

Not so fast.

The reality is that parts have tolerances, drift with age and are susceptible to temperature changes. What now? Does your circuit still meet all of your requirements?

In this blog, we provide a worst case circuit analysis on a power supply’s output power for a design that had been in use for several years, but started to see failures on units in the field. The end goal was to identify the worst case voltage outputs as part of a larger investigation to see if that could be the source of the failures.

The schematic was initially decomposed into manageable functional blocks to simplify the number of permutations for analysis, thus decreasing the number of simulation runs required for each section. For a schematic with N parts, the number of simulation permutations would be

Back to those three logical sections created.

These sections are extracted separately and transcribed into a SPICE simulation. The parts in each section are then indexed from 0 to n. Similar parts are grouped together with the same index to further reduce the number of runs required. For example, a group of series resistors can be combined since they will all have the same directional influence on the schematic. Each part or part group’s value is set up to switch between arbitrarily large max and min worst case values to determine the parts directionality (i.e. influence on the circuit when forced high or low). Exact tolerances at this stage are not important, as we just want to get an idea of which way the output changes based on changes to the parts value, and a big change is easier to see than a small change. We then iterate through the parts (based on their index) using the following SPICE directive:

This generates a series of plots (see below) that show, for example, simulated gains for each iteration.

Since the system will be operating at a set frequency well within the pass band of the circuit, we are not concerned about the frequency response of the system and just take the maximum gain for each of the iterations shown on the graph.

If, for example, there are 512 runs recorded, we would plot the min and max gains for each results in a graph like the one below. The X axis of the plot, when read as a binary value, corresponds to the directional state of each part.

In a 9 part simulation (2^9 = 512 values), X=50 (0 0011 0010 binary) indicates that the simulation run contained 3 parts at max value (corresponding 1’s) and 6 at min value (corresponding 0’s).

The maximum and minimum points on the graph correspond to the max and min gains that would be seen under a worst case scenario.

Once directionality has been established for all parts in each functional block, another simulation run is done using the independently computed worst case tolerances and another set of graphs will be generated.

The same process is repeated for subsequent logical stages where values from the prior stage are fed into the next stage to determine a final max/min output voltage. This process can be scaled to accommodate as many stages as necessary.

By running a final sweep, the nominal, max and min output voltages can be calculated. If the calculated max or mins are out of spec, the circuit can be refined focusing on the parts that contributed the most to the swing in output. This can help cut cost since only the most important contributing parts need to be swapped with higher tolerance parts.

If you need assistance in calculating your worst case circuit analyses, contact us. Our skilled team has over 30 years of providing top-notch engineering services to support and develop cost effective software, hardware and test solutions in a variety of industries, including aerospace, transportation, medical and more.

The schematic was initially decomposed into manageable functional blocks to simplify the number of permutations for analysis, thus decreasing the number of simulation runs required for each section. For a schematic with N parts, the number of simulation permutations would be

**2^N**(min and max of tolerance band for each part). By decomposing into three sections, the simulation permutations are reduced to**3 * 2^(N/3)**, if each section contains the same number of components. This dramatically reduces the overall run time of the simulations. Consider**N = 40**, a simulation of 1 trillion permutations that would be impossible to complete in our lifetimes is reduced to 31,000 runs which can easily be completed in a day or two.Back to those three logical sections created.

These sections are extracted separately and transcribed into a SPICE simulation. The parts in each section are then indexed from 0 to n. Similar parts are grouped together with the same index to further reduce the number of runs required. For example, a group of series resistors can be combined since they will all have the same directional influence on the schematic. Each part or part group’s value is set up to switch between arbitrarily large max and min worst case values to determine the parts directionality (i.e. influence on the circuit when forced high or low). Exact tolerances at this stage are not important, as we just want to get an idea of which way the output changes based on changes to the parts value, and a big change is easier to see than a small change. We then iterate through the parts (based on their index) using the following SPICE directive:

**.func wc(nom,tol,index) if(run==numruns, nom, if(binary(run,index), nom*(100+tol)/100, nom*(100-tol)/100))**This generates a series of plots (see below) that show, for example, simulated gains for each iteration.

Since the system will be operating at a set frequency well within the pass band of the circuit, we are not concerned about the frequency response of the system and just take the maximum gain for each of the iterations shown on the graph.

If, for example, there are 512 runs recorded, we would plot the min and max gains for each results in a graph like the one below. The X axis of the plot, when read as a binary value, corresponds to the directional state of each part.

In a 9 part simulation (2^9 = 512 values), X=50 (0 0011 0010 binary) indicates that the simulation run contained 3 parts at max value (corresponding 1’s) and 6 at min value (corresponding 0’s).

The maximum and minimum points on the graph correspond to the max and min gains that would be seen under a worst case scenario.

Once directionality has been established for all parts in each functional block, another simulation run is done using the independently computed worst case tolerances and another set of graphs will be generated.

The same process is repeated for subsequent logical stages where values from the prior stage are fed into the next stage to determine a final max/min output voltage. This process can be scaled to accommodate as many stages as necessary.

By running a final sweep, the nominal, max and min output voltages can be calculated. If the calculated max or mins are out of spec, the circuit can be refined focusing on the parts that contributed the most to the swing in output. This can help cut cost since only the most important contributing parts need to be swapped with higher tolerance parts.

If you need assistance in calculating your worst case circuit analyses, contact us. Our skilled team has over 30 years of providing top-notch engineering services to support and develop cost effective software, hardware and test solutions in a variety of industries, including aerospace, transportation, medical and more.